AI Compiler Engineer

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AI Compiler Engineer — Research Team

Austin, Texas

This is not a remote work opportunity.

MLIR Architecture | Compiler Infrastructure | 5G/6G Silicon | Bare-Metal AI
The Mission
Most AI compiler engineers optimize models for GPUs that already exist. You're going to optimize them for silicon that doesn't yet.

As our Senior AI Compiler Engineer, you're not porting a framework, tweaking a runtime, or wrapping CUDA libraries. You're doing something far rarer and far harder — building a complete MLIR-based compiler stack from the ground up, purpose-built to run massive AI models like Llama 3 on bare-metal 5G/6G telecommunications silicon, where there's no OS to bail you out and every byte of memory is accounted for.

The gap between a research model and hardware-optimized silicon execution is one of the most technically brutal problems in the industry right now. You'll be the engineer who closes it.

What You'll Actually Be Doing
MLIR Architecture — Own the Stack
You'll design and implement custom MLIR dialects from scratch — TableGen definitions, transformation passes, and the dialect conversion infrastructure that bridges the world of high-level AI graphs and the cold, hard reality of custom silicon. This is greenfield compiler work at its most consequential.

Lowering & Legalization — Zero Tolerance for Approximation
Take high-level computational graphs exported from JAX and StableHLO and lower them, step by step, into hardware-specific IR without losing a single bit of mathematical fidelity. Every op must legalize. Every semantic must survive the descent.

Concurrency & Memory Modeling — Orchestrate the Machine
There's no virtual memory here. No garbage collector. No safety net. You'll build static scheduling and tiling passes that choreograph data movement between HBM and on-chip local memory with surgical precision — because on this hardware, getting it wrong isn't a performance regression, it's a failure.

Production C++ — Code That Ships to Silicon
You'll maintain a high-performance, modular, LLVM-based compiler codebase where correctness and determinism aren't aspirational — they're required. This is production compiler engineering in the truest sense.

Join our Team

What You Bring

MLIR Mastery — You've built custom passes and dialect conversions, written TableGen definitions, and navigated the full complexity of the MLIR framework in a real production context
Compiler Fundamentals — Deep, hands-on C++ and LLVM expertise: IR structure, pass pipelines, and code generation pipelines that actually ship
Framework Integration — You've exported and lowered real models from JAX, PyTorch, or TensorFlow — you understand the gap between a research checkpoint and a deployable IR
Dialect Expertise — You know StableHLO or XLA at the op-semantics level, not just the API surface
What Makes You Exceptional:

Experience targeting Embedded DSP or VLIW architectures — instruction scheduling, register pressure, the works
Advanced optimization depth: loop tiling, vectorization, quantization lowering, fixed-point arithmetic
Hardware-level awareness of DMA engines, multi-level memory hierarchies, and complex number handling in MLIR — the stuff most compiler engineers never touch
Why This Role Is Different
This isn't a "make the existing thing faster" role. There is no existing thing. You'll be writing the compiler that a brand-new class of 5G/6G AI silicon runs on — and the decisions you make at the IR level will directly shape what that hardware can and can't do for the next generation of telecommunications infrastructure.

If you've ever wanted to work on a problem where the compiler, the hardware, and the research are all moving simultaneously — and where your code will eventually run at the edge of the global wireless network — this is that problem.